The present invention relates to a method of fabricating a textured tunnel oxide for an EEPROM(Electrically-Erasable Programmable Read-Only Memory) used in the production of VLSI, and in particular to a thin textured tunnel oxide prepared by thermal oxidation of a thin polysilicon film on a Si substrate (TOPS).
Thin tunnel oxides (.congruent.100 .ANG.) or thick polyoxides (oxides grown on polysilicon, .apprxeq.600A .ANG.) are typically used as tunneling gate dielectrics for EEPROMs. High density EEPROMs require scaling down device dimensions and lowering programming voltage. However, to write and erase the EEPROM cell with a lower voltage, the electron conductions in tunnel oxide must be enhanced. Scaling down the thin tunnel oxides for lower voltage operation may result in limitations in defect density, retention due to stress-induced leakages, or charge leakage due to direct tunneling. For thick polyoxides which use the rough polysilicon/oxide interface as an efficient electron injector, the very large electron trapping rate and memory window closing due to electron trapping will limit their memory endurance. Moreover, the reduction in thickness does not provide a proportional reduction in the programming voltage, because the electric field enhancement factor will decrease with the scaling-down of the polyoxide thickness.
Recently, Nozawa et al. has reported that tunnel oxides with a lower barrier height (.apprxeq.1.8 eV) could be obtained by thermally oxidizing the heavily implanted substrate (.gtoreq.10.sup.20 cm.sup.-3) in a diluted H.sub.2 0 ambient(H.sub.2 0+Ar)( H. Nozawa, N. Matsukawa, S. Morita, J.-I, Miyamoto and T. lizuka, "EEPROM cell with HB oxide for VLSI," VLSI Symp. Tech. Dig., p42, 1984; H. Nozawa, N. Matsukawa, and S. Morita, "An EEPROM cell using a low barrier height tunnel oxide," IEEE Trans, Electron Devices, vol. ED-33, p275,1986). The barrier height lowering effect of tunnel oxides grown on the heavily-doped substrate was attributed to the asperities, traps and arsenic clusters at the Si/SiO.sub.2 interface. However, more recently, Hegarty et al. indicated that thermal oxides grown on heavily-doped substrates would exhibit a very poor charge-to-breakdown(Q.sub.bd) characteristics(.ltoreq.10.sup.-2 C/cm.sup.2) and a very high electron trapping rate.( C. J. Hegarty, J. C. Lee, and C. Hu, "Enhanced conductivity and breakdown of oxides grown on heavily implanted substrate" Solid State Electron., vol. 34, p.1207, 1991).
Fong et al. has recently reported that thermal oxides (.apprxeq.230 .ANG.) grown on a textured single crystal silicon substrate(TSC oxide) could exhibit a remarkable field enhancement and concurrently possess good reliability and endurance characteristics ( Y. Fong, A. T. Wu, R. Moazzami, P. K. Ko, and C. Hu, "Oxides grown on textured single-crystal for low programming voltage non-volatile memory applications," IEDM Tech. dig. p. 889, 1987; Y. Fong, A. T. Wu, P. K. Ko, and C. Hu, "Oxides grown on textured single crystal silicon for enhanced conduction," Appl. Phys. Lett., vol.52, p 1139, 1988; Y. Fong, A. T. Wu, and C. Hu. "Oxides grown on textured single crystal silicon-dependence on process and application in EEPROMs," IEEE Trans. Electron Devices, vol. ED-37, p583, 1990). The TSC oxide exhibits a lower electron trapping rate than the thick polyoxide and better charge-to-breakdown(Q.sub.bd) characteristics than the normal oxide. However, the optimum texturization process must be performed by plasma etching or reactive ion etching(RIE) the As.sup.+ or Si.sup.+ implanted substrate through a sacrficial oxide, and the etched depth must be at least 500 .ANG. to obtain a satisfactory Q.sub.bd value. Also, the field enhancement factor decreases as the TSC oxide thickness decreases( M. Y. Hao and J. C. Lee, "Electrical Characteristics of oxynitrides grown on textured single-crystal silicon" Appl. Phys. Lett., Vol 60, p.445, 1992).